The present invention relates to a measurement structure in a standard cell for controlling and monitoring process parameters for electro-migration (EM) performance during manufacturing of an integrated circuit (IC).
Electro-migration (EM) refers to mass transport due to the momentum exchange between conducting electrons and diffusing metal atoms in metallic interconnects. As integrated circuits become progressively more complex, the individual components must become increasingly more reliable if the reliability of the whole device is to be acceptable. However, due to continuing miniaturization of very large scale integrated (VLSI) circuits, thin film metallic conductors or interconnects are subject to increasingly high current densities. Under these conditions, EM can lead to an electrical failure of a product within a relatively short time, therefore reducing the product lifetime to an unacceptable level. More and more integrated circuit systems, especially for those circuits used in medical, military, and space applications, need an assurance of system reliability for their critical missions. Therefore, it is of great importance and critical need to evaluate EM during the manufacturing process to assure overall chip reliability.
EM reliability tests during integrated circuit (IC) manufacturing attempt to project future EM failures, i.e., the tests calculate “EM projections”. Unfortunately, reliability of the tests is limited due to the approach used in conventional testing. For example, such tests are performed at extremely high temperatures (e.g., 300-400 degrees Celsius) in order to accelerate failure times of a very limited sample size (e.g., less than 100 samples per condition) at module level. Drawbacks of this approach include:
1) High temperatures could cause some competing degradation effects such as stress migration and low-k film material degradation;
2) Module (i.e., package) level test is costly as it requires, e.g., extra shipping, wafer dicing, cleaning, chiplet picking, wire bonding, baking, etc.; module level testing is also time consuming and prone to other damages, e.g., ESD, cracking, edge seal damages, etc.;
3) Modeling chip level EM from line level is not easy and needs a careful mathematical transformation (chip level EM is not Lognormal distributed); and
4) Confidence bounds of projection based on limited sample size are typically poor and multi-modal sub-group distributions cannot be easily separated from a limited sample size.